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SERESSA 2019 - 15th International School on the Effects of Radiation on Embedded Systems for Space Applications

  • Fechas:

    Del 02/12/19 al 05/12/19

  • Lugar:

    Centro Nacional de Aceleradores, c\ Thomas A. Edison, 7. 41092. Seville., Sevilla, España (mapa)

Web del evento

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Background

SERESSA combines academic, government, and industrial communities working in the area of radiation effects on embedded systems. Radiation effects are a significant concern for space and avionics systems, as well as for critical applications operating at ground level such as automotive, high energy facilities, medical or even banking. The school is based on lectures, exercises, and practical courses involving real case studies using the common tools of the domain. The intended audience includes both beginning and experienced researchers, engineers, and post-graduate students wishing to enhance their knowledge base in this rapidly evolving field. Topics covered by SERESSA include: radiation environment, spacecraft anomalies, single-event effects (SEE), total dose effects (TID), radiation effects in power systems, radiation effects in solar cells, architecture hardening in analog, and digital circuits and in memories, software hardening, effects in FPGAs, hardness assurance, rate prediction, radiation testing, laser testing and remote testing experiments.

 

 

SERESSA 2019 Participants will benefit with a 20% discount in the new book 'Radiation Effects on Integrated Circuits and Systems for Space Applications'.

More info: 'Registration Fees' tab

 

https://www.springer.com/gp/book/9783030046590

 

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[  P R E L I M I N A R Y  ]

2
Dic 2019
  • 07:30 - 08:15
    RECEPTION
  • 08:15 - 08:30
    OPENING SPEECHES
  • 08:30 - 09:30
    Space, Earth and Atmospheric Radiation Environments and their Main Effects in Electronic Devices

    The Sun and other stars are responsible of streams of particles in space that can affect electronic reliability. In this talk we focus on main sources (solar wind, solar flare, coronal mass ejection) and show how it induces radiations in Space. We also mention that some particles are trapped in the magnetic field of the Earth leading to harsh environment called radiation belts. These “cosmic rays” are also able to produce a radiation environment in atmosphere.

    Knowing the particles at play we will show briefly how they can interact with matter and that they are responsible of three kinds of failures in microelectronic device: ionizing dose, single event effects and displacement damages.

  • 09:30 - 10:30
    Accelerator radiation environment: modelling and monitoring tools and approaches

    The talk will describe the key features of the typical radiation environment of high energy physics accelerators, focusing on the case of the 27 km long Large Hadron Collider (LHC) at CERN. The key R2E challenges will be highlighted, and comparisons will be drawn with other known cases such as space applications or avionics. The talk will include examples of equipment affected by cumulative damage (mainly related to Total Ionising Dose) and Single Event Effects (SEEs). The latter are particularly critical for systems consisting of several distributed units along the LHC, and they pose a serious threat to the availability of the accelerator during operation.

  • 10:30 - 11:00
    COFFEE BREAK & POSTER SESSION
  • 11:00 - 12:00
    Radiation Effects Hardness Assurance for space missions

    The process by which parts are qualified for space in terms of radiation sensitivity will be described and illustrated with examples.

  • 12:00 - 13:00
    System Hardening and Real Applications

    This talk describes the suitable protections at architecture and system level against the effects of radiation on electronic components and digital systems. After the description of the general architecture of a space avionics system, the potential solutions for each type of units constituting an on-board computer are presented through the example of real space applications: avionics bus, links, memory units, and – the main part – processing units i.e. fault-tolerant architectures. The main fault-tolerant mechanisms are overviewed, as time replication either at instruction or task level, duplex, triplex (TMR), lock-step, and a trade-off between these different solutions. Then, real case studies are analyzed.

  • 13:00 - 14:30
    LUNCH
  • 14:30 - 15:30
    Effects of Radiation on Solar Cells

    This talk provides a brief introduction to solar cells, with emphasis in the state-of-the-art technology used for Space Applications. Some of the effects of particle radiation are analysed with the objective of predicting the degradation of these devices when used in space. In order to achieve this, the models commonly used in the prediction calculation are shown, and one of them is discussed in detail and applied to a particular case of a commercial solar cell.

  • 15:30 - 16:00
    COFFEE BREAK & POSTER SESSION
  • 16:00 - 17:00
    Automotive Functional Safety and Other Standards for Radiation Test Requirements

    Clair Cameron Patterson was the first person to estimate the age of the earth from the Canyon Diablo meteorite. He used the mass spectrometer at the Argonne National Laboratory with the isolated iron-meteorite troilite lead. The complete data yielded a Pb207/ Pb206 age of 4.55 + 0.07 billion years, and he published “Age of Meteorites and the Earth” paper in 1956. It was the first paper containing the true age of the solar system's accretion.

    As Clair tried for many years to eliminate effects from the lead, the lead still causes ongoing problems in our semiconductors. The trace materials from uranium and thorium in the semiconductor material generate enough alpha particles, which can produce equal or slightly less soft error rate than that of the neutrons at the sea level.

    The presentation will attempt to bring 4 key points to address current status of various standards requiring radiation test, how the data is analyzed and used, how the industry is preparing for the changes, and as an expert what and how can we help the businesses to achieve their goal of safety and the consumer to save money and provide reliability.

3
Dic 2019
  • 08:15 - 08:30
    ANNOUNCEMENTS
  • 08:30 - 09:30
    Single Event Effects (SEE): Mechanisms and Classifications

    The fundamental mechanisms responsible for non-destructive and destructive Single-Event Effects in ICs will be described in detail. This will include the interactions of ions with the constituent materials of the IC, the response of individual transistors to the disturbance, and the effect on the operation of the IC. The evolution of the threat with device scaling will be addressed. Radiation Effects Hardness Assurance The approach used to ensure that parts will meet performance requirements for a mission operating in a radiation environment will be discussed. A particular mission will be used to illustrate the method as applied to total ionizing dose, displacement damage dose and single event effects.

  • 09:30 - 10:30
    Fundamentals of the Pulsed-Laser Technique for Single-Event Effects Testing

    Carrier generation induced by pulsed-laser excitation has become an essential tool for the investigation of single-event effects (SEEs) of micro- and nano-electronic structures. The qualitative capabilities of this approach include, among others, sensitive node identification, radiation hardened circuit verification, basic mechanisms investigations, model validation and calibration, screening devices for space missions, and fault injection to understand error propagation in complex circuits. Recent effort has built upon the success enabled by these qualitative benefits, and has focused on putting the laser SEE approaches on a more quantitative basis. This presentation will present the basic physics associated with the single-photon and two-photon excitation processes, as well as numerous case studies illustrating the capabilities noted above.

  • 10:30 - 11:00
    COFFEE BREAK & POSTER SESSION
  • 11:00 - 12:00
    SEE effects on VLSI devices: ASIC and FPGA

    Radiation effects on VLSI technology are provoked when radiation particles such as neutrons, protons or heavy ions hit a sensitive region of the integrated circuits. Due to the progressive technology scaling, VLSI devices are becoming, more and more vulnerable to Single Event Effects (SEEs) and are subject to cumulative ionizing damage known as Total Ionization Dose (TID). This talk will firstly describe the state-of-the-art methodologies used for analysing the impact of radiation effects on modern FPGAs and ASICs by means of Computer Aided Design (CAD) tools and secondly, it will describe the state-of-the-art CAD design techniques for their mitigation.

  • 12:00 - 13:00
    Characterization, Modeling, and Analysis of Single Event Multiple Transient at Post-Layout level Using Satisfiability Modulo Theories

    In this talk, we will discuss the practical use of formal based techniques, such as SAT, SMT and probabilistic model checker to analyze SEEs at logical and higher abstraction levels. Through examples, we will illustrate each approach and its benefits.

  • 13:00 - 14:30
    LUNCH
  • 14:30 - 15:30
    Single Event Effects Test Methods

    The lecture presents an overview of main types of single event effects (SEE), basic characteristics of sensitivity of devices and integrated circuits to SEE and existing standards and guidelines for testing with the use of heavy ion and proton accelerators. Basic requirements for both heavy ion and proton testing will be considered in detail including requirements for the energy of ions, their linear energy transfer (LET) and the range in semiconductor, recommendations for choosing the flux and fluency of ions, requirements for beam control during testing. Also, the lecture gives information about the specifics of testing for different types of SEE, such as: an impact of temperature and electrical bias conditions on the test results; recommendations for choosing test patterns during testing; advantages and disadvantages of static and dynamic testing; an impact of total ionizing dose effects on test results; specifics of testing for destructive types of SEEs and others. In addition, the lecture presents some recommendations for choosing the SEE test algorithms depending on the purpose and required result of testing.

  • 15:30 - 16:00
    COFFEE BREAK & POSTER SESSION
  • 16:00 - 17:00
    New Developments in FPGA: SEUs and Fail-Safe Strategies

    Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being implemented. They range from weaker EDAC circuits that save area and power to strong mitigation strategies that come as a great expense to the system. Regarding FPGA and ASIC EDAC insertion, there is no “onesolution-fits-all.” The user must be aware of plethora of concerns. As an example, each FPGA devicetype requires a different mitigation strategy for various reasons. This presentation will focus on the susceptibilities of a variety of FPGA types and ASICs in the avionics and space environment. In addition, the user will be provided information on what are the optimal mitigation strategies per FPGA and ASIC. Internal device component mitigation versus system level mitigation will also be discussed.

4
Dic 2019
  • 08:15 - 08:30
    ANNOUNCEMENTS
  • 08:30 - 09:30
    Circuit Level Design Methods to Mitigate Soft Errors

    The mitigation of soft errors should be considered in all design abstraction levels, from high level to the physical one. This talk is focused in the circuit and physical design levels. Transistor reordering or transistor arrangements is an important way to improve robustness. The placement of serial transistors as far as possible to the cell output improves at least 4.9% the robustness of logic cells to the power variability, reaching 7% for the AOI21 cell. Another issue is the SET response under process variability using different transistor topologies. For all logic functions analyzed, regardless of the adopted topology, the LETth considering the WFF impact is smaller than the LETth at ideal conditions. That is, due to WFF, a smaller amount of energy transferred by the particle is required to cause a disturbance in the circuit. Circuit-Level hardening techniques are used to mitigate Soft Errors in FinFET gates.  For the near-threshold regime, the close topology is less sensitive than far topology for all levels of LET investigated. However, the gains of this technique are more significant for lower LETs. The same tendency was verified when decoupling cells were connected in the NAND2 output. The soft error mitigation can reach around 37% and 24.5% for a LET equal to 20MeV.cm2.mg-1when the AOI21 gate adopts the close topology, and the NAND2 adds the decoupling cells in the output, respectively. It is also done an evaluation of variability when using Schmitt Trigger on full adders’ layouts.  It is considered the process variability impact over several full adder layouts when using a Schmitt Trigger-based technique for robustness improvement. Simulations were performed at nominal and near-threshold operations. Circuits at near-threshold presented further improvements, in comparison to nominal values, with a maximum of 66.6% higher robustness. This and other Evaluation of Variability using Schmitt Trigger on Full Adders Layouts. It is considered the process variability impact over several Full Adder layouts with a Schmitt Trigger-based technique for robustness improvement. Simulations were performed at nominal and near-threshold operations. Circuits at near-threshold presented further improvements, in comparison to nominal values, with a maximum of 66.6% higher robustness. This and methods tom mitigate soft errors at circuit level, including layout ones will be presented.

  • 09:30 - 10:30
    Analyzing data extracted from radiation tests in advanced SRAMs

    When researchers perform experiments on advanced SRAMs in order to assess their sentivity against radiation, it is important to correctly classify the observed errors according to their multiplicity (Single Bit Upsets (SBUs), Multiple Cell Upsets (MCUs), etc). However, this might become a challenge in modern devices that implement mechanisms to detect and correct such errors (bit interleaving and Error Correcting Codes (ECC), amongst others). The reason is that this information is usually intellectual property (IP) of the manufacturers. In this talk we will discuss how this problem can be solved, even if said proprietary information is unkown to researchers. In addition, we will discuss the impact of error accumulation in experiments where too many bitflips are observed (due to a high particle flux, for example), and why the probability of observed so-called "false multiple events" is not negligible.

  • 10:30 - 11:00
    COFFEE BREAK & POSTER SESSION
  • 11:00 - 12:00
    Error-rate Prediction for Programmable Circuits: Methodology, Tools and Studied Cases

    This presentation describes a method devoted to SEU error-rate prediction for processor-based architectures. The proposed method combines results issued from fault-injection, performed at circuit by means of CEU (Code Emulated Upsets), to those issued from radiation ground tests. It allows predicting error rates without requiring radiation ground-tests for future applications. The approach was successfully applied to processors and FPGAs and is illustrated by three representative case-studies.

  • 12:00 - 13:00
    Fault Injection and Formal Verification Methodologies

    Fault injection is a widely used method to evaluate fault effects and error mitigation in a design. While not a replacement for standard Radiation‐Hardness Assurance methodologies, it can provide valuable information in a quick and inexpensive manner. Moreover, recent developments have improved performance by several orders of magnitude, thus enabling the realization of extremely large fault injection campaigns. Today, fault injection can be used to forecast the expected circuit behavior in the occurrence of SEUs and SETs and detect weak areas that require error mitigation. However, fault injection is not exhaustive. Thus, formal verification methods are needed to ensure that the design has no mitigation leaks. This talk will review the most relevant fault injection methods,covering software‐based techniques, simulation techniques and FPGA‐based emulation techniques. Recent advances for SET and MCU emulation will also be presented. Finally, formal verification techniques will also beintroduced.

  • 13:00 - 14:30
    LUNCH
  • 14:30 - 15:30
    Radiation Effects Testing and Modelling for Power Components in Accelerator Applications

    Due to their inherent destructive nature, Single Event Effects (SEE) on power components constitute one of the main concerns for the electronics used in accelerator applications. Following the authors experience in the study of SEE on power MOSFETs as a common thread, this talk covers several testing and modelling techniques, typically utilized to understand and prevent radiation-induced issues in silicon power MOSFETs and other power devices. In addition, the recent advances on the study of radiation effects on wide-bandgap devices (SiC, GaN), will be also addressed, accounting for the increasing interest of these highly-performance devices for accelerator applications.

  • 15:30 - 16:00
    COFFEE BREAK & POSTER SESSION
  • 16:00 - 17:00
    Enhanced Observation Framework for Embedded Systems exposed to Radiations

    In the first part of this talk, we present an embedded error classifier for Soft Error Rate characterization of cells under radiations. It is implemented on top of flip-flop chains and embedded in a test-chip. It allows classifying errors among two categories, Single-Event Upset (SEU) and Single-Event Transient (SET) depending on the area under strikes. We describe its implementation and the added value of this solution. In the second part, we present an embedded observation IP based on on-chip trace buffering to improve the observability of RISC-V Core under radiations.

  • 20:00 - 6 Dic 23:00
    SOCIAL DINNER
5
Dic 2019
  • 08:15 - 08:30
    ANNOUNCEMENTS
  • 08:30 - 09:30
    EEE Parts in the New Space Paradigm

    As the space business rapidly evolves to accommodate a lower cost model of development and operation via concepts such as commercial space and small spacecraft (aka, CubeSats and swarms), traditional EEE parts screening and qualification methods are being scrutinized under a risk reward trade space. In this presentation, two basic concepts will be discussed: The movement from complete risk aversion EEE parts methods to managing and/or accepting riskvia alternate approaches; and discussion of emerging assurance methods to reduce overdesign as well emerging model based mission assurance (MBMA) concepts. Example scenarios will be described as well as consideration for trading traditional versus alternate methods.

  • 09:30 - 10:30
    COTS in Space: Constraints, Limitations and Disruptive Capability

    This talk describes one application of CNES methodology for allowing to use commercial (COTS) digital electronic components in large spacecrafts. The required steps the components have to successfully pass before to be authorized to fly are presented. Then, the limitation concerning COTS usable performance is outlined. Even if these specificities reduce the attractiveness of commercial components, several project configurations are highlighted where COTS components are a feasibility factor for the space mission due to their contribution to system performance.

  • 10:30 - 11:00
    COFFEE BREAK & POSTER SESSION
  • 11:00 - 12:00
    COTS in Space: Qualified Commercial Components for Space

    Commercial electronics compared to their space qualified counterparts are increasingly proving to be fit for use in space. High performance and reliability together with reduction of qualification costs and less testing time play an important role in the development of the space market. SpaceCOTS are commercial components qualified for small satellite missions, which support the NewSpace technology development.

  • 12:00 - 13:00
    The Phoenix GPS Receiver for Rocket and Satellite Applications: An Example for the Successful Utilization of COTS Technology in Space Projects

    This talk aims to provide a practical example of the successful application of an entirely COTS-based GPS receiver in various space projects such as sounding rocket flights and LEO satellites missions. Almost any Earth-orbiting satellite mission planned and realized during the last two decades has, at any point, considered to employ a GNSS receiver as part of the satellite. However, for the majority of these projects, a fully space-qualified GNSS receiver is out of reach due to the extremely high costs typically associated with such hardware. For projects with a more limited budget the use of a COTS-based version of the desired device is typically the only viable alternative. Driven by this motivation, DLR’s space flight technology group has commenced to explore, develop and test COTS-based GPS sensors about 20 years ago. As an outcome of this work, among others, the Phoenix GPS receiver for space applications has been developed, tested and finally made available to numerous small- and mid-scale space projects. In this talk, the Phoenix GPS receiver will be introduced in more detail. An overview about the conducted space qualification program and the so far gathered flight heritage of the sensor will be provided.

  • 13:00 - 14:30
    LUNCH
  • 14:30 - 15:30
    COTS for Deep Space Missions

    The usage of COTS in Deep Space Missions might be an increased risk for the missions. But sometimes are radiation tolerant parts not feasible due to space, performance or power requirements. In that case, the usage of COTS could be a possible solution. This talk gives an brief overview of the usage of COTS in (Deep) Space Missions at the DLR Institute of Robotics and Mechatronics and the associated radiation assurance activities.

  • 15:30 - 16:00
    COFFEE BREAK & POSTER SESSION
  • 16:00 - 17:00
    Transient Faults in Spaceborne Delay Tolerant Networks: Intrinsic Robustness & Smart Re-routing

    Internet-based communications have profoundly affected day to day life on Earth, and nothing seems to impede the exploitation of its advantages in near Earth constellations, deep-space missions, and beyond. However, delay (provoked by signal propagation) and disruption (provoked by planet occlusion or platforms and energy constraints) are the rule in space networking. Thus, the underlying protocols for the future space Internet rely on the Delay and Disruption Tolerant Networking (DTN) paradigm, where instantaneous feedback can no longer be assumed. In this talk we argue that by being delay-tolerant, the DTN architecture exhibits an intrinsic fault-tolerant feature. However, fault events need to be properly modeled and considered in the end-to-end DTN routing approach. After revising relevant missions in the domain, we discuss how recent research have treated transient faults as another case of disruptions in DTN. Nonetheless, while disruptions provoked by orbital mechanics are deterministic, transient faults exhibit a probabilistic behavior, and thus, require a different modeling approach at the routing level. Appropriate modeling based on Markov Decision Processes is presented and considered in the context of DTN routing decisions, to finally highlight opportunities and open research issues in the domain.

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